Design of High-Speed Communication Circuits (Selcted Topics by Ramesh Harjani

By Ramesh Harjani

MOS know-how has swiftly develop into the de facto regular for mixed-signal built-in circuit layout end result of the excessive degrees of integration attainable as machine geometries cut back to nanometer scales. The aid in characteristic measurement implies that the variety of transistor and clock speeds have elevated considerably. actually, present day microprocessors comprise thousands of thousands of transistors working at a number of gigahertz. moreover, this aid in function measurement additionally has an important impression on mixed-signal circuits. as a result of the better degrees of integration, the vast majority of ASICs possesses a few analog parts. It has now turn into approximately obligatory to combine either analog and electronic circuits at the related substrate because of fee and gear constraints. This ebook offers the various more moderen difficulties and possibilities provided by way of the small machine geometries and the excessive degrees of integration that's now attainable. the purpose of this e-book is to summarize the most serious features of high-speed analog/RF communications circuits. recognition is concentrated at the effect of scaling, substrate noise, facts converters, RF and instant verbal exchange circuits and wireline conversation circuits, together with high-speed I/O.

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Wooley, "Design Techniques for High-Speed, High-Resolution Comparators", IEEE J. Solid-State Circuits (Dec 1992) 1916—1926. 22. H. Pan, M. Segami, M. Choi, J. Cao, and A. A. 6-um CMOS with over 80-dB SFDR," IEEE Journal of Solid-State Circuits, vol. 35, pp. (Dec 2000) 1769 - 1780. 23. K. Kattmann and J. Barrow, "A technique for reducing differential non-linearity errors in flash A/D converters," IEEE International Solid-State Circuits Conference, vol. 34, pp. (Feb 1991) 170 - 171. 24. H. Pan and A.

This represents a resistive connection between the supplies and the current flow here too is independent of the nature of output transition. Finally, impact ionization in the NMOS devices (Iim) also contributes to current flow through the local ground tie. As pointed out earlier, this current is physically unidirectional. When dedicated substrate pins are used instead of local substrate connections to ground and supply (for NMOS and PMOS devices respectively), the nature of current flow into the substrate pins is substantially different from the above case.

The first is the computation time required for substrate extraction mentioned above. The second issue relates to efficient use of the extracted models. An N contact problem leads to 0(N 2 ) simulation elements in the circuit simulator. For a practical IC, it is not feasible to attempt a full scale simulation of this order. Approximations can be employed to partition the problem into smaller sections. Coarse-fine approximation techniques can be employed where the impact of distant contacts is not considered in detail 6 ' 7 .

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